1. Field of the Invention
The present invention relates to a differential amplifier circuit and particularly a differential amplifier circuit having two input stages including transistors of different conductivity types.
2. Description of the Related Art
Dimensions of MOSFETs realized on LSIs are continuously reduced due to the progress in the LSI fabrication technique in recent years, and this results in the decrease of maximum voltage applicable to the MOSFETs. Furthermore, a requirement for the power supply voltage reduction has been increasing in various mobile electronic apparatuses as a result of increased performance requirements and demands with respect to the mobile electronic apparatuses, the progress made in batteries and peripheral components, and the social needs to save energy.
The reduction in the power supply voltage undesirably makes it more difficult to operate and design electronic circuits of electronic apparatuses. One problem is that the allowed input voltage range of enhancement type NMOS or PMOS FETs, which are widely used in an LSI with the CMOS configuration, is limited. In detail, an enhancement type FET has an invalid voltage range in which the output current is not turned on (such characteristics are often called normally-off) More specifically, an NMOS transistor can work with an input voltage higher than the threshold voltage thereof, whereas a PMOS transistor can work with an input voltage lower than the negative threshold voltage which is obtained by reducing the threshold voltage from the power supply voltage. In contrast, the ratio of the threshold voltage with respect to the power supply voltage increases when the power supply voltage is reduced; this implies that the ratio of the prohibited voltage range with respect to the power supply voltage increases. Otherwise, a signal voltage in the circuit is reduced below the threshold voltage level, resulting in a malfunction of the circuit.
One promising approach to solve this problem is to incorporate both of an input transistor pair of NMOS transistors and an input transistor pair of PMOS transistors in a differential amplifier circuit. FIG. 1 is a circuit diagram showing a typical configuration of a differential amplifier circuit such structured. The circuit configuration of FIG. 1 is disclosed by Behzad Razavi in “Design of Analog CMOS Integrated Circuits”, McGraw-Hill, 2002, pp. 326, for example.
A differential amplifier circuit 100 of FIG. 1 includes an N-type input stage 101, a P-type input stage 102 and an output stage 103. The N-type input stage 101 includes NMOS transistors M11 to M13, and the P-type input stage 102 includes PMOS transistors M14 to M16. The NMOS transistor M12 and the PMOS transistor M14 are connected to a non-inverted input terminal IP which receives one of differential input signals (i.e. non-inverted input signal), while the NMOS transistor M13 and the PMOS transistor M15 are connected to an inverted input terminal IM which receives the other differential input signal (i.e. inverted input signal). That is, the NMOS transistors M12 and M13 in the N-type input stage 101 constitute a NMOS transistor pair which receives the differential input signals, while the PMOS transistors M14 and M15 in the P-type input stage 102 constitute a PMOS transistor pair which receive the differential input signals.
The output stage 103 includes NMOS transistors M17 to M1A and PMOS transistors M1B to M1E. The nodes N11 and N12 in the output stage 103 are connected to drains of the PMOS transistors M14 and M15 in the P-type input stage 102, respectively, while the nodes N14 and N15 in the output stage 103 are connected to the drains of the NMOS transistors M12 and M13 in the N-type input stage 101, respectively. The output stage 103 outputs from the output terminal OUT an output signal corresponding to the differential input signals fed to the N-type input stage 101 and the P-type input stage 102.
Enhancement type transistors (which are normally-off) may be used for the NMOS transistors and the PMOS transistors in the differential amplifier circuit 100.
In the differential amplifier circuit 100 of FIG. 1, the N-type input stage 101, which is configured with the NMOS transistors M12 and M13, is allowed to receive an input voltage equal to or higher than the threshold voltage of the NMOS transistors, whereas the P-type input stage 102, which is configured with the PMOS transistors M14 and M15, is allowed to receive an input voltage equal to or lower than the voltage which is obtained by reducing the threshold voltage of the PMOS transistors from the power supply voltage. Accordingly, the differential amplifier circuit 100 of FIG. 1 is capable of handling an input voltage in the entire voltage range from ground to the power supply voltage.
However, the inventor of the present invention has found a problem that the offset voltage of the differential amplifier circuit 100 of FIG. 1 is not set to zero. A detail discussion is given of this problem in the following. In the following discussion, all the MOS transistors in the differential amplifier circuit 100 are assumed to be operated in the saturation region unless it is explicitly stated otherwise. It should be noted that the assumption that all the MOS transistors are operated in the saturation region does not make a substantial inaccuracy from the actual operation of the differential amplifier circuit 100 for the purpose of the explanation of the concept of the circuit operation.
In general, the drain current ID of a MOS transistor is expressed by the following Equation (1):
                    ID        =                                            μ              ⁢                                                          ⁢              Cox                        2                    ·                      W            L                    ·                                    (                              VGS                -                Vth                            )                        2                    ·                      (                          1              +                              VDS                                  V                  ⁢                                                                          ⁢                  A                                                      )                                              (        1        )            where μ is carrier mobility in the channel, Cox is the gate capacitance per unit area, W is the gate width, L is the gate length, VGS is the gate-source voltage, Vth is the threshold voltage, VDS is the drain-source voltage, and VA is the Early voltage.
For easy analysis and understanding of the circuit, all the NMOS transistors and PMOS transistors are assumed to have the same gain factor β (=μCox*W/L), the same threshold voltage Vth and the same Early voltage VA in the following. The following notations are defined:                Ix: the drain current of the MOS transistor Mx (x =11 to 1E);        VGSx: the gate-to-source voltage of the MOS transistor Mx;        VDSx: the drain-to-source voltage of the MOS transistor Mx;        VNy: the voltage level of the node Ny (y=13);        VIP: the voltage level of the non-inverted input signal (i.e. the voltage level of the non-inverted input terminal IP);        VIM: the voltage level of the inverted input signal (i.e. the voltage level of the inverted input terminal IM); and        VO: the output voltage (i.e. the voltage level of the output terminal OUT).        
In the differential amplifier circuit 100 of FIG. 1, the offset voltage of zero means that the following Equation (2) is established if VIP is equal to VIM:VO=VDD/2,  (2)where VDD is the power supply voltage.
The output voltage VO is expressed by the following Equation (3) which is derived from Equation (1):
                                                        VO              =                            ⁢                                                Rout                  ·                                      (                                                                  I                        ⁢                                                                                                  ⁢                        1                        ⁢                                                                                                  ⁢                        C                                            -                                              I                        ⁢                                                                                                  ⁢                        1                        ⁢                        A                                                              )                                                  +                                  VDD                  2                                                                                                        =                            ⁢                                                Rout                  ·                                      (                                                                  I                        ⁢                                                                                                  ⁢                        1                        ⁢                                                                                                  ⁢                                                  B                          ·                                                                                    VDD                              -                              VO                                                                                      VDD                              -                                                              VN                                ⁢                                                                                                                                  ⁢                                13                                                                                                                                                        -                                              I                        ⁢                                                                                                  ⁢                                                  19                          ·                                                      VO                                                          VN                              ⁢                                                                                                                          ⁢                              13                                                                                                                                            )                                                  +                                  VDD                  2                                                                                                        =                            ⁢                                                                    Rout                    ·                                          (                                                                                                    VDD                            -                            VO                                                                                VDD                            -                                                          VN                              ⁢                                                                                                                          ⁢                              13                                                                                                      -                                                  VO                                                      VN                            ⁢                                                                                                                  ⁢                            13                                                                                              )                                        ·                    I                                    ⁢                                                                          ⁢                  1                  ⁢                                                                          ⁢                  B                                +                                  VDD                  2                                                                                                        ≈                            ⁢                                                                    Rout                    ·                                          (                                                                                                    VDD                            -                            VO                                                                                VDD                            -                                                          VN                              ⁢                                                                                                                          ⁢                              17                                                                                                      -                                                  VO                                                      Vth                            ⁢                                                                                                                  ⁢                            17                                                                                              )                                        ·                    I                                    ⁢                                                                          ⁢                  1                  ⁢                                                                          ⁢                  B                                +                                  VDD                  2                                                                                        (        3        )            where Rout is the output resistance of the differential amplifier circuit 100 measured from the output terminal OUT.
The first term of Equation (3) is not reduced down to zero even when the transistors in the differential amplifier circuit 100 have the same properties. That is, even when the properties of the PMOS transistors M14 and M15 in the P-type input stage 102 are exactly identical, the properties of the NMOS transistors M12 and M13 in the N-type input stage 101 are exactly identical, and the threshold voltages of the PMOS transistors and the NMOS transistors are exactly identical, Equation (2) is not established as an identical equation; Equation (2) is established only in a special case where Vth17=VO. In other words, the offset voltage of the differential amplifier circuit shown in FIG. 1 is not always set to zero. When the properties of the transistors therein are not identical (e.g. the input stages include transistors with different properties), the offset voltage further deviates from zero.